ASIC Digital Design

 Clock gating technique is to reduce dynamic power dissipation. Enable signal based clock gating Latch based clock gating (Integrated Clock Gating)

 For the active high reset, input zero is given to the input of the reset synchronizer.

 1. RTL FIX : 2. Reset Ordering : When reset1 is asserted then reset2 is also asserted. 3. Clock gating: 4. Waiver/Constraints:                                reset_order {r1, r2}

 A clock domain crossing occurs whenever data is transferred from a flop driven by one clock to a flop driven by another clock. Fig : Clock domain Crossing Two Flop Synchronizer Two flop synchronizer is used for synchronizing a single bit level signal. It converts the signal from source clock domain to destination clock domain. Two stage flop synchronizer is shown below: Fig : Two flop synchronizer Slow to Fast Pulse Synchronizer Fast to Slow Pulse Synchronizer Handshake Synchronizer

FIFO: FIFO stands for First In First Out. The process of writing in FIFO is called Push. The process of reading out of FIFO is called Pop. Types of FIFO: i.  Synchronous FIFO ii. Asynchronous FIFO Empty & Full Condition: Empty Condition: wrptr = rdptr Full Condition: wrptr = 1 1 1 + 1 = 1 0 0 0 rdptr                    = 0 0 0 0    {~wrptr[3] , wrptr [2:0]} = {rdptr[3:0]}    FIFO Depth Calculation: CASE I : NO IDLE CYCLE Given, Writing Frequency (FA)  = 100 MHz Reading Frequency (RD) = 50  MHz Burst Length = No of data item to be transferred  = 100 Calculate the minimum depth of the FIFO. 1. Time required to write one data item = 1/100 * 1000  = 10 ns 2. Time required to write  all data in the burst = (100*10) = 1000 ns 3. Time required to read one data item = 1/50 * 1000 = 20 ns 4. The number of data item that can be read in a duration of 1000 ns = 1000ns/20ns = 50 5. The remain...

Setup Time: The setup time is the interval before the clock where the data must be held stable. Hold Time: The hold time is the interval after the clock where the data must be held stable. Setup and Hold Time Violation Setup time violation: It is because when a signal arrives too late. Hold time violation: It is because when an input changes too quickly. If the setup and hold parameters are violated, the output would either logic 0, logic 1 or metastable state. To avoid setup time violation:  T(ctoq) + Tcomb + Tsetup - Tskew < Tperiod Setup Slack =   Tperiod - ( T(ctoq) + Tcomb + Tsetup - Tskew) I.   Decreasing the clk to q delay of the launching flop. II.  Decreasing the propagation delay of the combinational logic. III. Reducing the setup time requirement of the capturing flop. IV. Increasing the skew between capture and launch clock. V. Increasing the clock period. To avoid hold time violation:  T(ctoq) + Tcomb >  Thold + Tskew Hold Slack...