Static Timing Analysis

Setup Time:

The setup time is the interval before the clock where the data must be held stable.

Hold Time:

The hold time is the interval after the clock where the data must be held stable.

Setup and Hold Time Violation

Setup time violation:

It is because when a signal arrives too late.

Hold time violation:

It is because when an input changes too quickly.

If the setup and hold parameters are violated, the output would either logic 0, logic 1 or metastable state.

To avoid setup time violation: 

T(ctoq) + Tcomb + Tsetup - Tskew < Tperiod

Setup Slack =  Tperiod - (T(ctoq) + Tcomb + Tsetup - Tskew)

I.   Decreasing the clk to q delay of the launching flop.

II.  Decreasing the propagation delay of the combinational logic.

III. Reducing the setup time requirement of the capturing flop.

IV. Increasing the skew between capture and launch clock.

V. Increasing the clock period.

To avoid hold time violation: 

T(ctoq) + Tcomb > Thold + Tskew

Hold Slack = T(ctoq) + Tcomb - Thold - Tskew

I.   Increasing the clk to q delay of the launching flop.

II.  Increasing the propagation delay of the combinational logic.

III. Decreasing the hold requirement of the capturing flop.

IV. Decreasing the skew between the capture and launch flop.

Slack:

Slack is defined as the difference between actual time and the desired time for a timing path.

Setup Slack:

T(ctoq) + Tcomb + Tsetup - Tskew < Tperiod

Setup Slack =  Tperiod - (T(ctoq) + Tcomb + Tsetup - Tskew)

Hold Slack:

T(ctoq) + Tcomb > Thold + Tskew

Hold Slack = T(ctoq) + Tcomb - Thold - Tskew

NOTE:

• The +ve slack means design is working at the specified frequency and it has some more margin as well.
• The zero slack specifies design is exactly working at the specified frequency and there is no margin available.
• The -ve slack implies that design doesn't achieve the constrained frequency and timing. This is called timing violation.

Skew:

Skew is the arrival of a clock signal at the clock input of different flip flops at different time as a result of propagation delay.

Problem : Calculate the maximum clock frequency

Given,

Tclktoq = 9 ns

Tcomb  = 13 ns

Tsetup   = 5 ns

Thold    = 4 ns

Tbuf     =  2 ns

Clock Period (T) =   T(ctoq) + Tcomb + Tsetup - Tskew

                            = 9 ns + 13 ns + 5 ns - 2ns = 25 ns

Hence,

Maximum Frequency (Fmax) = 1/25 ns = 40 MHz