Reset Domain Crossing
1. RTL FIX :
2. Reset Ordering :
When reset1 is asserted then reset2 is also asserted.
3. Clock gating:
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4. Waiver/Constraints:
reset_order {r1, r2}
2X1 Multiplexer
Boolean Equation Y = I0 if {S = 0} Y = I1 if {S = 1} Truth Table Dataflow Modeling module mux_21(I0,I1,S,Y); input I0,I1,S; output Y; assign Y = (S)?I1:I0; endmodule Behavioral Modeling module mux_21(I0,I1,S,Y); input I0,I1,S; output Y; reg Y; always@(I0 or I1 or S) begin if(S == 1'b1) Y = I1; else Y = I0; end endmodule Case Statement module mux_21(I0,I1,S,Y); input I0,I1,S; output Y; reg Y; always@(I0 or I1 or S) begin case(S) 1'b1 : Y = I1; 1'b0 : Y = I0; endcase end...
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