ASIC Digital Design

 

 Clock gating technique is to reduce dynamic power dissipation. Enable signal based clock gating Latch based clock gating (Integrated Clock Gating)

 For the active high reset, input zero is given to the input of the reset synchronizer.

 1. RTL FIX : 2. Reset Ordering : When reset1 is asserted then reset2 is also asserted. 3. Clock gating: 4. Waiver/Constraints:                                reset_order {r1, r2}

 A clock domain crossing occurs whenever data is transferred from a flop driven by one clock to a flop driven by another clock. Fig : Clock domain Crossing Two Flop Synchronizer Two flop synchronizer is used for synchronizing a single bit level signal. It converts the signal from source clock domain to destination clock domain. Two stage flop synchronizer is shown below: Fig : Two flop synchronizer Slow to Fast Pulse Synchronizer Fast to Slow Pulse Synchronizer Handshake Synchronizer