Mealy State Machine:1001
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Design
module mealy_machine(clk,rst,din,dout);
input clk,rst,din;
output dout;
reg dout;
reg [3:0] state;
parameter s0 = 4'b0001,
s1 = 4'b0010,
s2 = 4'b0100,
s3 = 4'b1000;
always@(posedge clk or negedge rst)
begin
if(rst == 1'b0)
begin
state <= s0;
dout <= 1'b0;
end
else
begin
case(state)
s0:
begin
if(din == 1'b1)
begin
state <= s1;
dout <= 1'b0;
end
else
begin
state <= s0;
dout <= 1'b0;
end
end
s1:
begin
if(din == 1'b1)
begin
state <= s1;
dout <= 1'b0;
end
else
begin
state <= s2;
dout <= 1'b0;
end
end
s2:
begin
if(din == 1'b1)
begin
state <= s1;
dout <= 1'b0;
end
else
begin
state <= s3;
dout <= 1'b0;
end
end
s3:
begin
if(din == 1'b1)
begin
state <= s1;
dout <= 1'b1;
end
else
begin
state <= s0;
dout <= 1'b0;
end
end
endcase
end
end
endmodule
Testbench
module mealy_machine_tb;
reg t_clk,t_rst,t_din;
wire t_dout;
mealy_machine mealy_machine_tb(.clk(t_clk),
.rst(t_rst),
.din(t_din),
.dout(t_dout)
);
initial
begin
t_clk = 0;
forever #10 t_clk =~t_clk;
end
initial
begin
t_rst = 1'b0;
t_din = 1'b0;
#10
t_rst = 1'b1;
t_din = 1'b1;
#20
t_din = 1'b0;
#20
t_din = 1'b0;
#20
t_din = 1'b1;
end
initial
begin
$monitor("%t, t_din=%b, t_dout=%b",$time, t_din, t_dout);
end
endmodule
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